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Showing posts with label Georgia Virtual Post Office Mailbox | Digital Mail. Show all posts
Showing posts with label Georgia Virtual Post Office Mailbox | Digital Mail. Show all posts
by Frabricio Ruiz on Sunday 12 February 2023 07:31 AM UTC-05
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by noreply@blogger.com (Loni Cardon) on Sunday 12 February 2023 12:34 AM UTC-05
Obituary – Alan Lynn Anderson ... Alan Lynn Anderson was born May 14, 1964, in San Antonio, Texas, and passed away suddenly of natural causes on Jan. 27 ...
by Houston Texas Appliance Parts on Friday 10 February 2023 03:21 PM UTC-05
AI in chip design has gone mainstream, with Synopsys' AI-powered DSO (design space optimization) tool reaching 100 commercial tapeouts.
The company's DSO was released in 2020, with its first commercial tapeout in August 2021. The tool uses reinforcement learning to tackle physical layout optimization—that is, all the physical aspects of chip design.
"This technology has seen very fast adoption over the past two and a half years," Stelios Diamantidis, distinguished architect at Synopsys, told EE Times. "Importantly, [the 100 tapeouts] are across design nodes, across vertical markets and with very high coverage of the semiconductor leaders."
Synopsys expects "hundreds" more tapeouts this year, according to Diamantidis. The EDA company is working with customers designing cutting-edge chips, including CPUs, GPUs and AI accelerators, with new applications continuing to emerge.
Stelios Diamantidis (Source: Synopsys)
Synopsys customer SK Hynix was able to not only increase productivity using DSO, but also reduced die size for one of its designs by 5%. This 5% silicon area improvement can mean a considerable economic benefit, given that memory products are produced in the tens or hundreds of millions, Diamantidis said.
The tool's first 100 tapeouts includes the first commercial tapeout using the cloud-based version of DSO—an STMicroelectronics 7-nm FinFET design. ST said physical layout optimization for a new Arm core was 3× faster in terms of both time-to-result and engineering time spent on the design using DSO.
"We used the tools to accelerate the physical design of a key IP block that we integrated into an ASIC," Indavong Vongsavady, methods, tools and infrastructure director of the RF and communication division at STMicroelectronics, told EE Times. "As is true for highly complex designs, we don't have a one-size-fits-all approach to the design. We use different tools and approaches for different pieces and in this case, given DSO's ability to let us perform lots of experiments in a short period of time to optimize performance, power and area, it made sense to use it on a particular block of IP."
Using DSO during the design authoring process allowed ST to achieve a higher level of optimization than usual, he said, adding that ST is confident that the product will meet quality criteria during the normal verification and final sign-off process.
"We think that AI/ML algorithms are a good fit when we have extremely challenging optimization problems to solve," Vongsavady added. "The best way to solve these is using a huge number of experiments, and this is where the DSO.ai tool shines because it offloads the burden of mechanical tasks and gives our engineers more time for creative thinking."
The decision to use DSO in Microsoft's Azure cloud was made largely for flexibility and convenience; ST performed tens to hundreds of parallel runs on 16 or 32 CPU cores, peaking at a few thousand CPU cores.
"The cloud enhances our storage and compute capacity, and we exploited that elasticity in our use of the tool," Vongsavady said. "We can access as much server and CPU capacity as we need for massive parallel experiments without the risk of impacting other ST projects running on-premises."
Reinforcement learning
DSO uses a technique called reinforcement learning to tackle physical layout. The problem is complex; place and route alone has a state space of 10 to the power of 90,000. Reinforcement learning is a good fit since it doesn't require masses of data for training. This would mean having access to Synopsys' customers' chip designs, which are proprietary. Instead, the algorithm can be trained by designing chips from scratch and being given a score for how well it does. Over time, the algorithm tries over and over to achieve a better score.
Part of DSO's secret sauce is the ability to also learn from completed designs. In this case, customers would use their own existing designs to train their version of algorithm via supervised learning, as a way of using knowledge of prior designs. This can help the AI converge faster on an optimum design.
While much of the focus of the AI industry in general has been on transformers and large language models lately, Synopsys' Diamantidis said reinforcement learning is definitely the best fit for this application.
"We continue to see tremendous value in reinforcement learning," he said. "Comparing DSO in 2020 to the 2023 version, there is a clear evolution of technology as we ourselves become smarter and more research emerges that we can leverage."
While reinforcement learning will continue to be impactful both in EDA and other applications, it isn't the only horse in the race. Synopsys is interested in possible combinations with other learning paradigms, such as generative AI and graph networks, but reinforcement learning will continue to be the backbone, Diamantidis said.
"We may not have big data, which is generated out in the wild and we get to go out and mine it, but we do have what [machine learning pioneer] Andrew Ng calls 'good data,' which is we understand the origin of the data and can make some assumptions about its classification and behavior and that gives us some advantages that again play to reinforcement learning's strengths."
Synopsys will also continue to develop its statistical learning (non-AI) tools, according to Diamantidis.
Chip customization
Aart de Geus (Source: Synopsys)
One of the key downstream effects of AI-powered chip design is to make the ASIC model more attractive since it means more quickly and easily taping out customized versions of ASICs for particular verticals or customers. Other downstream effects of designing better performing chips on vastly condensed timescales with less engineering resource include prolonging Moore's law by squeezing better performance from older process nodes, and accelerating entry to market for companies without chip design experience.
This is what DSO can achieve today, but what's next for AI-powered EDA tools? Synopsys CEO Aart de Geus gave some hints in his keynote at ISSCC 2022, in which he talked about using AI to more efficiently remaster silicon designs for different process nodes, or different foundries. (This is a future technology; DSO's remastering capability doesn't have any commercial tapeouts yet).
In an interview with EE Times at the time, de Geus said that AI-powered remastering has the potential to help ease fab capability issues. The trick is using learning from the original chip design when remastering the chip for a different node, rather than starting from scratch.
"It was quite remarkable how the learning from [a tapeout at] N40 was absolutely still applicable in N10, which is 3 nodes more advanced," he said. "This tells me that certain characteristics of the design really determine its essence: its bottlenecks, what makes the speed, what makes the power and so on."
Versus a human-designed chip remastered for N10, the AI-designed version was faster and more power efficient, but also took less time to design.
Experimental results of remastering a design for a different process node. Red triangle is the results of manual design by a team of experts over a period of months. Yellow diamonds are designs produced by an AI with no training on the new target node, but with knowledge of the design on the old node. These results were produced by a single engineer in a matter of weeks. (Source: Synopsys)
"Something else is coming out of these experiments: the notion that if you are using high tech, which is fast-moving, but for products that have a long life cycle, you should start designing some of those products such that if you had to make a new version of it, you already captured the learning or the spec in such a way that in seven years it can be designed more easily," he added.
Not only can AI design better chips than human engineers, but we will need AI to keep up with future increases in device complexity—just like we needed design automation 35 years ago, de Geus said. The number of dimensions that need to be optimized is growing, including speed, area, dynamic power, static power, reliability, manufacturability and yield.
"One way that humans design when they don't know the exact answer is they put in margin," he said. "AI can find itsy bitsy little margin pieces all over the place, and so maybe it's a very small piece that it finds, but it finds 3 billion of them, and you can see the human challenge with that."
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by noreply@blogger.com (Loni Cardon) on Thursday 09 February 2023 07:34 PM UTC-05
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by Houston Texas Appliance Parts on Thursday 09 February 2023 02:21 AM UTC-05
As demand for high-performance semiconductors increases, the semiconductor market is paying more attention to the importance of the "packaging process". In line with this trend, SK hynix is mass-producing advanced packaging products based on HBM3 (High Bandwidth Memory 3) while focusing on investing in production lines and securing resources for the development of future packaging technologies. Some businesses that have previously focused on technology for semiconductor memory manufacturing are investing more in packaging technology than OSAT1 companies that specialize in such technology. This trend is driven by the belief that packaging technology will strengthen the competitiveness of the semiconductor industry and the companies within it.
1OSAT (Outsourced Semiconductor Assembly and Test): A company that specializes in semiconductor packaging and testing.
This articlewillprovide an accessible overview ofpackaging technology, whichhas beenconsideredadifficulttopicforthegeneralpublicto approachdue to itscomplexity.The meaning, role, and evolution of packagingtechnologywill be examined,followed byalook intothedevelopment ofSKhynix'spackaging technologythat has ledto the current focus on heterogeneous integration. Finally,the direction ofthe company'sfuture technological developmentswill be introduced.
TheMeaning andRole ofPackagingTechnology
First, let's look at the four main functions of the packaging process. The first and most basic purpose is to protect the semiconductor chip from external shock or damage. The second is to transmit external power to the chip for its operation,andthe third is to provide wiring for the chip to perform the input and output of electrical signals during operation.The lastroleis toproperlydistribute the heat generatedbythe chip to ensure stable operation. Recently, the function of heat dissipation, or heat distribution, has become increasingly important.
The role of packaging can beseeninFigure 1. For example, there is a significant gap between thescalerequired by the system and the scale provided by CMOS2,but theycan be connected through packaging technology. Similarly, there is agap between the density required by the system and thedensitythat CMOS can provide. This issuecan be resolved through the packaging processas it helpsincrease the densityof the CMOS.In otherwords, packaging technology acts as a bridge between semiconductor devices and systems.The importance of thisconnection method, therefore,increasesgradually.
2CMOS (Complementary Metal Oxide Semiconductor): An integrated circuit design on a printed circuit board (PCB) that uses semiconductor technology.
Figure 1. Memory packaging bridges the scale gap between the devices and the system
Three Stages of Packaging Development: Stack Competition, Performance Competition, and Convergence
When examining the history of packaging technology, it can be divided into three majoreras. In the past,asinglepackagewouldonly implement one chip. Consequently,packages were simple and had nodistinguishing factors, and the value added by packaging technology was low. However, in the early 2000s, with theswitchto FBGA3packaging, the stacking of multiple chips on one package began. Thiscan bereferred to as the "Era of Stacking Competitiveness."As chips began to be stacked, the form of the packagediversifiedand various derivative products were created depending on the combination ofthememory chips. The MCP4,whichimplements DRAMand NAND in the same package, also appeared at this time.
3FBGA (Fine Pitch Ball Grid Array): A type of surface-mount packaging (a chip carrier) used for integrated circuits based on ball grid array technology. It has thinner contacts and is mainly used in system-on-a-chip designs.
4MCP (Multi Chip Package): A product made into a single package by vertically stacking two or more different types of memory semiconductors.
The secondera beganafter 2010 when a method of interconnection using a bump on a chip appeared. As a result,changes inthe operating speedand thedevicepropertymarginsoccurred.Thisperiodcan becalledthe"Era of Performance Competitiveness"aspackaging technology prior to 2010generallyinvolvedconnectingmetal wires, but theintroductionof bumps shortenedthe signal path to achieve faster speeds. Meanwhile, the stacking method usingTSV5drastically increases the number of I/Os(Input/Output), which leadstoconnecting1,0246wide I/Osenabling high operating speedseven in low voltage.In thisera of performance competitiveness, thepropertiesof chips changeaccording to thepackaging technology, andthisbecomes an importantfactorinfulfilling the requirements of thecustomers.Asthe success or failure of a businesscandepend on the presence or absence of packaging technology, the value of packaging technology hascontinued togrow.
The third and finalera began in2020andisbased on all the previouspackaging technologies.Itcan beconsideredthe"Convergence Era" as it requires technology that can connect various types of chips intoone package and, also, connectmany partsinto one modulewhenincorporatinga system.In this era,packaging technology itself can become a system solution, and customized packaging solutions can be provided to customerstomakesmall quantity batch production possible.At this point,merelyowning packaging technology will determine the success of a business.
5TSV (Through-Silicon Via): Interconnection technology that drills thousands of fine holes in DRAM chips and connects the holes of the upper and lower layers with electrodes that penetrate vertically.
61,024: Standard DRAM has up to 64 I/Os, whereas HBM3 has a maximum of 1,024 wide I/Os.
Figure 2. Changes due to the development of packaging technology
History of SKhynix'sPackagingTechnology
SKhynix'spackaging technologyunderwent significantdevelopmentthroughout theaforementionederas.Although the company's packaging technology was not significantly differentiatedup to the stacking competitiveness era, as the performance competitiveness era began,SKhynixbecamerenowned for itspackaging technology.In particular,CoC7technology,which combinesbumpinterconnection andwirebonding,usheredininnovationthat includesfaster speedsandreducedcosts.Itiscurrently a specialized technology applied in the production and manufacturing of SKhynix'shighdensitymodules.Additionally, SKhynixhas developedMR-MUF8technologyand has been applyingitto HBM products.This technologyimproves thequality in more than 100,000 micro bump interconnections of HBM.In addition, this packagingtechnologyhas sufficiently increased the number of thermal dummy bumpswhile excelling in heat dissipation compared to its competitors as itappliesamoldedunderfill(MUF)material which hashigh thermal conductivity.This advancement has helped SKhynixincrease its share of the HBM market and eventually take a leadingposition in the HBM3 sector.
7CoC (Chip-on-Chip): A packaging technology designed to electrically connect two (or more) dies together without the need for TSV (Through-Silicon Via).
8MR-MUF (Mass Reflow Molded Underfill): MR-MUF refers to the process of attaching semiconductor chips to circuits and filling the space between chips and the bump gap with a material called 'liquid EMC' (Epoxy Molding Compound) when stacking up chips. So far, NCF technology has been used for this process. NCF is a method of stacking chips by using a kind of film between chips. The MR-MUF method has about twice the thermal conductivity compared to NCF and affects the process speed as well as the yield.
Today, inthe convergence era, SKhynixis promoting the developmentof Hybrid Bonding technology which uses Cu–to–Cu bonding9instead of soldering.Moreover,the company is reviewing multipleoptions for applying various packaging technologies includinggraftingtheFan-out RDL10technology.Hybrid Bonding technologyallows forfiner pitches11and, accordingly, has the advantage in terms of the height of the packaging as it is a gapless bonding technique that does not usesolderbumps when stacking chips.In addition,Fan-out RDL technologyis applicable to various platforms,soSKhynixplans to useitwhenincorporatingpackageswithChiplet12. Linepitch andmulti-layer are keycomponents ofFan-out technology, and SKhynixaims to secure RDL technology below 1 micron,or at sub-micron level,by 2025.
9Cu-to-Cu (Copper-to-Copper) Bonding: One of the hybrid bonding methods of the packaging process, which provides a solution for 10µm pitches and below by completely avoiding the use of bumps. Direct copper-to-copper connections are applied in this process when dies in packages need to be connected to each other.
10RDL (Redistribution Layer): An extra metal layer on an integrated circuit that reroutes its I/O pads in other desired locations of the chip, for better access to the pads where necessary. For example, a bump array located in the center of a chip can be redistributed to positions near the chip edge. The ability to redistribute points can enable higher contact density and enable subsequent packaging steps.
11Pitch: Minimum center-to-center distance between interconnect lines
12Chiplet: Technology that divides chips by use such as controller or high-speed memory, and manufactures them as separate wafers before re-connecting them in the packaging process
Figure 3. SK hynix's Latest Packaging Technology
Packaging technology will become an important means ofprovidingholisticsystem solutionsthat gobeyond one-dimensional functionssuch aschipprotectionandsupplying power.It won't be long before companies will need topossesspackaging technologyto become aleaderinthe semiconductorindustry.Several years ago, amajorfoundry company inEast Asianot only created a new system-in-package (SiP) business through a technology calledintegratedfan-out(InFO)packaging, butit wasalsoable toincreasethe existing business area offoundry sales—which has great implications forSKhynix.Just as thiscompanyis known for itsproduction ofcontrollers,SKhynixisrenownedforproducinghigh-performancesemiconductormemoriessuch asitsHBM. SKhynixalso developed advanced packaging technologies such asheterogenous integrationand fan-out RDL technology—key packaging technologies in the upcoming convergence era.Consequently, the companyisnot only playinga role as a memory-integrateddevicemanufacturer (IDM) butis also becomingatotal"solutionprovider"thatcanlead the future semiconductormemoryindustry.
